module arbiter_divider(
    input  wire             clk,       // 输入时钟
    input  wire             rst_n,     // 异步复位(低有效)
    input       [31:0]      div_factor,
    output reg              div_clk,    // 分频后时钟
    
    
    input                   direction,
    output                  wave_a_out,
    output                  wave_b_out
    
);


reg [31:0] cnt;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt     <= 0;
        div_clk <= 0;
    end else begin
        if (cnt < div_factor - 1)
            cnt <= cnt + 1;
        else
            cnt <= 0;

        // 50% duty cycle logic
        if (cnt < div_factor/2)
            div_clk <= 1;
        else
            div_clk <= 0;
    end
end


reg [31:0]  cnt1;
reg         wave_a;
reg         wave_b;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt1    <= 0;
        wave_a <= 0;
        wave_b <= 0;
    end else begin
        if (cnt1 < div_factor - 1)
            cnt1 <= cnt1 + 1;
        else
            cnt1 <= 0;

        // wave_a: high for first half, low for second half
        if (cnt1 < div_factor/2)
            wave_a <= 1;
        else
            wave_a <= 0;

        // wave_b: high for middle half, low for first and last quarters (90-degree phase shift)
        if ((cnt1 >= div_factor/4) && (cnt1 < 3*div_factor/4))
            wave_b <= 1;
        else
            wave_b <= 0;
    end
end

assign wave_a_out = direction ? wave_a : wave_b;
assign wave_b_out = direction ? wave_b : wave_a;

endmodule